The present disclosure relates to synchronous/clocked digital circuits, and more specifically, to the management of power consumption of a gated clock mesh within an integrated circuit (IC).
Synchronous digital circuits are circuits in which the data states of memory elements are synchronously updated in response to a clock signal received by the memory elements. Circuit delay can be introduced throughout a clock distribution circuit in order to ensure that all memory elements are clocked and subsequently capture their respective data within a specified time interval. As IC circuit performance becomes faster, and the tolerances for the arrival time of clock signals at memory elements become tighter, clock distribution circuit delays can be increasingly affected by IC manufacturing process variations. Such variations can cause functionally similar and physically proximate circuit elements to exhibit significantly different propagation delays. To manage and mitigate these delay variations, signal timing margins may need to be increased significantly in order to protect circuits against signal timing violations. Clock distribution schemes that include clock meshes can be used to provide relatively uniform, low-skew clock distribution to digital memory and logic elements within an IC. Clock mesh structures can also be used to provide tighter on-chip delay tolerances relative to those provided by conventional clock tree designs.